Digital Library
A HIGHLY SECURE FPGA-BASED DUAL-HIDING ASYNCHRONOUS-LOGIC AES ACCELERATOR AGAINST SIDE-CHANNEL ATTACKS
JavaScript is disabled for your browser. Some features of this site may not work without it.
| dc.contributor.author | JOSEPH, ALSA | |
| dc.date.accessioned | 2023-02-21T04:57:08Z | |
| dc.date.available | 2023-02-21T04:57:08Z | |
| dc.date.issued | 2022-12-15 | |
| dc.identifier.uri | http://hdl.handle.net/123456789/10829 | |
| dc.language.iso | en | en_US |
| dc.title | A HIGHLY SECURE FPGA-BASED DUAL-HIDING ASYNCHRONOUS-LOGIC AES ACCELERATOR AGAINST SIDE-CHANNEL ATTACKS | en_US |
| dc.type | Technical Report | en_US |
