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| dc.contributor.author | MARIA VARGHESE, AVINO | |
| dc.date.accessioned | 2023-02-16T05:09:52Z | |
| dc.date.available | 2023-02-16T05:09:52Z | |
| dc.date.issued | 2022-07-28 | |
| dc.identifier.uri | http://hdl.handle.net/123456789/10815 | |
| dc.language.iso | en | en_US |
| dc.title | DESIGN OF A SCALABLE LOW POWER 1 BIT HYBRID FULL ADDER FOR FAST COMPUTATION | en_US |
| dc.type | Technical Report | en_US |
