<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:dc="http://purl.org/dc/elements/1.1/" version="2.0">
<channel>
<title>S2 SEMINAR REPORT</title>
<link>http://hdl.handle.net/123456789/10652</link>
<description/>
<pubDate>Sun, 05 Apr 2026 21:44:20 GMT</pubDate>
<dc:date>2026-04-05T21:44:20Z</dc:date>
<item>
<title>DELAY MONITORING SYSTEM WITH MULTIPLE GENERIC MONITORS FOR WIDE VOLTAGE RANGE OPERATION</title>
<link>http://hdl.handle.net/123456789/10692</link>
<description>DELAY MONITORING SYSTEM WITH MULTIPLE GENERIC MONITORS FOR WIDE VOLTAGE RANGE OPERATION
P S, SILPA
</description>
<pubDate>Thu, 29 Jul 2021 00:00:00 GMT</pubDate>
<guid isPermaLink="false">http://hdl.handle.net/123456789/10692</guid>
<dc:date>2021-07-29T00:00:00Z</dc:date>
</item>
<item>
<title>3D SRAM WITH MONOLITHIC INTEGRATION TECHNOLOGY</title>
<link>http://hdl.handle.net/123456789/10691</link>
<description>3D SRAM WITH MONOLITHIC INTEGRATION TECHNOLOGY
S NAIR, SURAJ
</description>
<pubDate>Thu, 29 Jul 2021 00:00:00 GMT</pubDate>
<guid isPermaLink="false">http://hdl.handle.net/123456789/10691</guid>
<dc:date>2021-07-29T00:00:00Z</dc:date>
</item>
<item>
<title>RINGNET: A MEMORY ORIENTED NETWORK ON CHIP DESIGNED FOR FPGA</title>
<link>http://hdl.handle.net/123456789/10690</link>
<description>RINGNET: A MEMORY ORIENTED NETWORK ON CHIP DESIGNED FOR FPGA
T A, FATHIMA
</description>
<pubDate>Thu, 29 Jul 2021 00:00:00 GMT</pubDate>
<guid isPermaLink="false">http://hdl.handle.net/123456789/10690</guid>
<dc:date>2021-07-29T00:00:00Z</dc:date>
</item>
<item>
<title>AN ULTRASOUND BASED BIOMEDICAL SYSTEM FOR CONTINUOUS CARDIOPULMONARY MONITORING</title>
<link>http://hdl.handle.net/123456789/10688</link>
<description>AN ULTRASOUND BASED BIOMEDICAL SYSTEM FOR CONTINUOUS CARDIOPULMONARY MONITORING
L S, SREELAKSHMI
</description>
<pubDate>Thu, 29 Jul 2021 00:00:00 GMT</pubDate>
<guid isPermaLink="false">http://hdl.handle.net/123456789/10688</guid>
<dc:date>2021-07-29T00:00:00Z</dc:date>
</item>
</channel>
</rss>
