<?xml version="1.0" encoding="UTF-8"?>
<rdf:RDF xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns="http://purl.org/rss/1.0/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#">
<channel rdf:about="http://hdl.handle.net/123456789/9227">
<title>MIXED SIGNAL VLSI DESIGN</title>
<link>http://hdl.handle.net/123456789/9227</link>
<description/>
<items>
<rdf:Seq>
<rdf:li rdf:resource="http://hdl.handle.net/123456789/9283"/>
<rdf:li rdf:resource="http://hdl.handle.net/123456789/9281"/>
<rdf:li rdf:resource="http://hdl.handle.net/123456789/9280"/>
<rdf:li rdf:resource="http://hdl.handle.net/123456789/9279"/>
</rdf:Seq>
</items>
<dc:date>2026-04-05T19:01:17Z</dc:date>
</channel>
<item rdf:about="http://hdl.handle.net/123456789/9283">
<title>MIXED SIGNAL VLSI DESIGN 05EC 6002 (JUL 2021)</title>
<link>http://hdl.handle.net/123456789/9283</link>
<description>MIXED SIGNAL VLSI DESIGN 05EC 6002 (JUL 2021)
</description>
<dc:date>2021-07-30T00:00:00Z</dc:date>
</item>
<item rdf:about="http://hdl.handle.net/123456789/9281">
<title>MIXED SIGNAL VLSI DESIGN 05EC 6002 (MAY 2019)</title>
<link>http://hdl.handle.net/123456789/9281</link>
<description>MIXED SIGNAL VLSI DESIGN 05EC 6002 (MAY 2019)
</description>
<dc:date>2019-05-31T00:00:00Z</dc:date>
</item>
<item rdf:about="http://hdl.handle.net/123456789/9280">
<title>MIXED SIGNAL VLSI DESIGN 05EC 6002 (APR 2018)</title>
<link>http://hdl.handle.net/123456789/9280</link>
<description>MIXED SIGNAL VLSI DESIGN 05EC 6002 (APR 2018)
</description>
<dc:date>2018-04-28T00:00:00Z</dc:date>
</item>
<item rdf:about="http://hdl.handle.net/123456789/9279">
<title>MIXED SIGNAL VLSI DESIGN 05EC 6002 (S) (DEC 2017)</title>
<link>http://hdl.handle.net/123456789/9279</link>
<description>MIXED SIGNAL VLSI DESIGN 05EC 6002 (S) (DEC 2017)
</description>
<dc:date>2017-12-30T00:00:00Z</dc:date>
</item>
</rdf:RDF>
