<?xml version="1.0" encoding="UTF-8"?>
<rdf:RDF xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns="http://purl.org/rss/1.0/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#">
<channel rdf:about="http://hdl.handle.net/123456789/10800">
<title>A HIGHLY SECURE FPGA-BASED DUAL-HIDING ASYNCHRONOUS-LOGIC AES ACCELERATOR AGAINST SIDE-CHANNEL ATTACKS</title>
<link>http://hdl.handle.net/123456789/10800</link>
<description/>
<items>
<rdf:Seq>
<rdf:li rdf:resource="http://hdl.handle.net/123456789/10829"/>
</rdf:Seq>
</items>
<dc:date>2026-04-05T18:56:21Z</dc:date>
</channel>
<item rdf:about="http://hdl.handle.net/123456789/10829">
<title>A HIGHLY SECURE FPGA-BASED DUAL-HIDING ASYNCHRONOUS-LOGIC AES ACCELERATOR AGAINST SIDE-CHANNEL ATTACKS</title>
<link>http://hdl.handle.net/123456789/10829</link>
<description>A HIGHLY SECURE FPGA-BASED DUAL-HIDING ASYNCHRONOUS-LOGIC AES ACCELERATOR AGAINST SIDE-CHANNEL ATTACKS
JOSEPH, ALSA
</description>
<dc:date>2022-12-15T00:00:00Z</dc:date>
</item>
</rdf:RDF>
