<?xml version="1.0" encoding="UTF-8"?>
<rdf:RDF xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns="http://purl.org/rss/1.0/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#">
<channel rdf:about="http://hdl.handle.net/123456789/10012">
<title>DESIGN AND VERIFICATION OF ‘N’ POINT FFT AND IFFT USING VERILOG</title>
<link>http://hdl.handle.net/123456789/10012</link>
<description/>
<items>
<rdf:Seq>
<rdf:li rdf:resource="http://hdl.handle.net/123456789/10041"/>
</rdf:Seq>
</items>
<dc:date>2026-04-05T20:08:52Z</dc:date>
</channel>
<item rdf:about="http://hdl.handle.net/123456789/10041">
<title>DESIGN AND VERIFICATION OF ‘N’ POINT FFT AND IFFT USING VERILOG</title>
<link>http://hdl.handle.net/123456789/10041</link>
<description>DESIGN AND VERIFICATION OF ‘N’ POINT FFT AND IFFT USING VERILOG
j, ADITHYAN; P, ABHIRAM; PAUL, ASHER; V S, SRUTHY
</description>
<dc:date>2021-07-30T00:00:00Z</dc:date>
</item>
</rdf:RDF>
