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<title>VLSI</title>
<link href="http://hdl.handle.net/123456789/7076" rel="alternate"/>
<subtitle/>
<id>http://hdl.handle.net/123456789/7076</id>
<updated>2026-04-05T17:42:04Z</updated>
<dc:date>2026-04-05T17:42:04Z</dc:date>
<entry>
<title>VLSI</title>
<link href="http://hdl.handle.net/123456789/11263" rel="alternate"/>
<author>
<name/>
</author>
<id>http://hdl.handle.net/123456789/11263</id>
<updated>2023-05-10T21:30:10Z</updated>
<published>2023-03-02T00:00:00Z</published>
<summary type="text">VLSI
</summary>
<dc:date>2023-03-02T00:00:00Z</dc:date>
</entry>
<entry>
<title>VLSI</title>
<link href="http://hdl.handle.net/123456789/11261" rel="alternate"/>
<author>
<name/>
</author>
<id>http://hdl.handle.net/123456789/11261</id>
<updated>2023-05-10T21:30:09Z</updated>
<published>2023-02-02T00:00:00Z</published>
<summary type="text">VLSI
</summary>
<dc:date>2023-02-02T00:00:00Z</dc:date>
</entry>
<entry>
<title>VLSI EC 304 (R&amp;S) (JIL 2021)</title>
<link href="http://hdl.handle.net/123456789/8005" rel="alternate"/>
<author>
<name/>
</author>
<id>http://hdl.handle.net/123456789/8005</id>
<updated>2022-06-27T22:15:16Z</updated>
<published>2021-07-30T00:00:00Z</published>
<summary type="text">VLSI EC 304 (R&amp;S) (JIL 2021)
</summary>
<dc:date>2021-07-30T00:00:00Z</dc:date>
</entry>
<entry>
<title>VLSI EC 304 (S) (SEP 2020)</title>
<link href="http://hdl.handle.net/123456789/8003" rel="alternate"/>
<author>
<name/>
</author>
<id>http://hdl.handle.net/123456789/8003</id>
<updated>2022-06-27T22:15:16Z</updated>
<published>2020-09-30T00:00:00Z</published>
<summary type="text">VLSI EC 304 (S) (SEP 2020)
</summary>
<dc:date>2020-09-30T00:00:00Z</dc:date>
</entry>
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