DESIGN OF A SCALABLE LOW POWER 1 BIT HYBRID FULL ADDER FOR FAST COMPUTATION http://hdl.handle.net/123456789/10788 2026-04-05T20:40:54Z 2026-04-05T20:40:54Z DESIGN OF A SCALABLE LOW POWER 1 BIT HYBRID FULL ADDER FOR FAST COMPUTATION MARIA VARGHESE, AVINO http://hdl.handle.net/123456789/10815 2023-02-16T21:30:09Z 2022-07-28T00:00:00Z DESIGN OF A SCALABLE LOW POWER 1 BIT HYBRID FULL ADDER FOR FAST COMPUTATION MARIA VARGHESE, AVINO 2022-07-28T00:00:00Z